1. Field of the Invention
The present invention relates to phase locked loop ICs. More particularly, it relates to a phase-locked loop IC which is well suited to a magnetic disk storage device of the type transferring data at high speed, and an information processing system having such a magnetic disk storage device.
2. Description of the Related Art
In, for example, a magnetic disk storage device in the prior art, a phase locked loop circuit which generates a synchronizing clock for reproducing recorded data is usually constructed of a PLL (Phase-Locked Loop) shown in FIG. 25.
Referring to the figure, a phase comparator 1 compares the phases of a data signal 5 and a VCO clock (synchronizing clock) 10 which is produced by a voltage-controlled oscillator (abbreviated to "VCO") 4. When the phase of the data signal 5 leads over that of the VCO clock 10, the comparator 1 delivers an INC (increase) signal 6 for a corresponding time period, whereas when the former lags the latter, it delivers a DEC (decrease) signal 7.
Upon receiving the INC signal 6 or the DEC signal 7, a charge pump 2 performs a charge operation responsive to the INC signal 6 or a discharge operation responsive to the DEC signal 7.
A loop filter 3 integrates and smooths the output 8 of the charge pump 2 so as to generate a VCO control voltage 9. The VCO 4 produces the VCO clock 10 at a frequency corresponding to the VCO control voltage 9.
The phase locked loop circuit operates in this manner, thereby bringing the phase of the VCO clock 10 into agreement with that of the data signal 5.
Constants indicating the response characteristics of the PLL include a characteristic frequency Wn and an attenuation factor .xi.. These constants are determined by such conditions as an initial phase difference and a phase capture time Taq.
Here, assuming that the length of each pattern to be synchronized is fixed, the phase capture time Taq depends upon the transfer rate of data, because the phase of the VCO clock must be captured within the time span of the pattern to be synchronized.
The phase-locked loop circuit of the magnetic disk storage in the prior art has the characteristic frequency Wn set high and the attenuation factor .xi. set small in order to complete the phase lock capture within the time span of the pattern to be synchronized.
Then, after the completion of the phase-lock capture, the phase-locked loop circuit has the characteristic frequency Wn set lower and the attenuation factor .xi. set greater than in the phase-lock capture process in order to stably phase-lock the VCO clock 10 to random data patterns.
In the prior art magnetic disk storage, the rotational speed of a magnetic disk is ordinarily set at 3,600 r.p.m., and the length of each pattern to be synchronized at 11 bytes or so.
With the recent progress of recording tecnology, etc., the recording density has been increased year by year. At present, even a storage device which has a recording density exceeding 26,000 b.p.i. is available as a commercial product.
Here, the data transfer rate of a 5.increment. disk becomes about 15 Mb.p.s. under the conditions of the rotational speed of 3,600 r.p.m. and recording density of 26,000 b.p.i.
Besides, the capture time becomes about 3.2 .mu.s in order to capture the phase of the VCO clock for each 6 byte pattern to be synchronized under the above specifications.
In the phase-locked loop circuit, the free-running oscillation frequency of the VCO 4 is set at a value conformed to the data transfer rate. In this regard, the loop circuit is contrived so as to widen the phaselockable capture frequency range (a capture range) as much as possible, taking into consideration situations where the freerunning oscillation frequency of the VCO 4 deviates from the set value on account of the temperature characteristics, the supply voltage characteristics, etc. of the circuit, and where the cycle of the patterns to be synchronized changes due to the rotational fluctuation, etc. of the magnetic disk. Moreover, in the magnetic disk storage device, the cycle of the read data signal fluctuates greatly relative to its expected value on account of magnetic interference, etc. Therefore, the loop circuit is contrived so as to similarly widen a phase lockable follow-up frequency range (a lock range) as much as possible.
The single-chip LSIs of phase locked loop circuits intended to cope with the high speed data transfer of the magnetic disk storage device, are currently on the market. However, the highest data transfer rates of these single chip LSIs are 15 Mb.p.s. to 24 Mb.p.s.
Regarding large sized magnetic disk storage device, there is an example wherein a phase locked loop circuit is constructed of discrete components of rapid ECL, thereby realizing the highest data transfer rate of 36 Mb.p.s.
Meanwhile, PLL frequency synthesizers, etc. conformed to high frequencies for use in communication equipment, etc. are on the market, and the signal frequencies to be dealt with are generally higher as compared with those of the magnetic disk storage device.
In a communication system, however, the high speed capture as in the magnetic disk storage device is not required. Moreover, since the quality of the data signal is comparatively good, it is not necessary to secure a wide capture range and a wide lock range.
At present, many kinds of products which can conform to 180 MHz or higher frequencies are commericially available as PLL frequency synthesizers.
In recent years, however, a higher operating speed has been increasingly required of the whole information processing system. As regards magnetic disk storage, for example, included in the system, it has become an important technical objective to heighten the data transfer rate thereof, as well as enlarging the memory capacity thereof.
Therefore, it has also become common practice to realize a higher data transfer rate by raising the rotational speed of the magnetic disk beyond the ordinary value of 3,600 r.p.m.
In general, the magnetic disk storage device has a fixed write frequency. In order to attain the larger memory capacity, however, zone-bit recording wherein the write frequency is varied radially on the magnetic disk has been devised and has already been put into practical use in some examples.
With the zone-bit recording, the write frequency is made unequal at the inner and outer peripheral parts of the magnetic disk, whereby the recording density is optimised as much as possible so as to enlarge the memory capacity. Consequently, the data transfer rate changes depending on the radial position of the data on the magnetic disk, and it becomes higher at the outer peripheral part than at the inner peripheral part.
The data transfer rate should desirably be heightened by adopting the higher speed rotation or the new recording technique in this manner. When the higher speed rotation and the new recording technique are conjointly utilized, the data transfer rate can be greatly increased, as has been the case in recent developments.
Nevertheless, regarding the phase-locked loop circuit in the prior art, at the highest level of present-day technology, the single-chip LSI can only attain its highest data transfer rate of 32 Mb.p.s. or so, and the circuit arrangement configured of the discrete components of rapid ECL etc. can achieve the highest data transfer rate of 36 Mb.p.s. Since these have been realized for use in magnetic disk storage. Data transfer at a still higher rate has not yet actually been attained.